lib/src/pcidef.h File Reference
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Define Documentation
| #define BASE_ADDR_BELOW_1MB 1 |
| #define BASE_ADDR_RESERVED 3 |
| #define ERRTAG_K_PCIERR 16 |
| #define PCI_K_AUDIO_CTRLR 1 |
| #define PCI_K_BASE_ADDRESS_0 16 |
| #define PCI_K_BASE_ADDRESS_1 20 |
| #define PCI_K_BASE_ADDRESS_2 24 |
| #define PCI_K_BASE_ADDRESS_3 28 |
| #define PCI_K_BASE_ADDRESS_4 32 |
| #define PCI_K_BASE_ADDRESS_5 36 |
| #define PCI_K_BASE_CLASS 11 |
| #define PCI_K_BRIDGE_DEVICE 6 |
| #define PCI_K_CACHE_LINE_SIZE 12 |
| #define PCI_K_CARDBUS_CIS 40 |
| #define PCI_K_DEVICE_ID 2 |
| #define PCI_K_DEVSEL_FAST 0 |
| #define PCI_K_DEVSEL_MEDIUM 1 |
| #define PCI_K_DEVSEL_SLOW 2 |
| #define PCI_K_DISPLAY_CTRLR 3 |
| #define PCI_K_EISA_BRIDGE 2 |
| #define PCI_K_EXP_ROM_BASE 48 |
| #define PCI_K_FDDI_CTRLR 2 |
| #define PCI_K_FLOPPY_CTRLR 2 |
| #define PCI_K_HEADER_TYPE 14 |
| #define PCI_K_HOST_BRIDGE 0 |
| #define PCI_K_IDE_CTRLR 1 |
| #define PCI_K_INTR_LINE 60 |
| #define PCI_K_INTR_PIN 61 |
| #define PCI_K_INTR_PIN_INTA 1 |
| #define PCI_K_INTR_PIN_INTB 2 |
| #define PCI_K_INTR_PIN_INTC 3 |
| #define PCI_K_INTR_PIN_INTD 4 |
| #define PCI_K_INTR_PIN_NOT_USED 0 |
| #define PCI_K_IPI_CTRLR 3 |
| #define PCI_K_ISA_BRIDGE 1 |
| #define PCI_K_LATENCY_TIMER 13 |
| #define PCI_K_MASS_STORAGE_CTRLR 1 |
| #define PCI_K_MAX_DEVICES 32 |
| #define PCI_K_MC_BRIDGE 3 |
| #define PCI_K_MEMORY_CTRLR 5 |
| #define PCI_K_MULTIMEDIA_DEVICE 4 |
| #define PCI_K_NETWORK_CTRLR 2 |
| #define PCI_K_NOT_IMPLEMENTED 0 |
| #define PCI_K_OTHER_BRIDGE 80 |
| #define PCI_K_OTHER_DISPLAY 80 |
| #define PCI_K_OTHER_MASS_STORAGE 80 |
| #define PCI_K_OTHER_MEMORY 80 |
| #define PCI_K_OTHER_MULTIMEDIA 80 |
| #define PCI_K_OTHER_NETWORK 80 |
| #define PCI_K_PCI_PCI_BRIDGE 4 |
| #define PCI_K_PCMCIA_BRIDGE 5 |
| #define PCI_K_PROGRAMMING_IF 9 |
| #define PCI_K_REVISION_ID 8 |
| #define PCI_K_SCSI_CTRLR 0 |
| #define PCI_K_SUB_CLASS 10 |
| #define PCI_K_SUB_VNDR 44 |
| #define PCI_K_TOKEN_CTRLR 1 |
| #define PCI_K_UNDEFINED 255 |
| #define PCI_K_VENDOR_ID 0 |
| #define PCI_K_VGA_CTRLR 0 |
| #define PCI_K_VIDEO_CTRLR 0 |
| #define PCI_K_XGA_CTRLR 1 |
| #define PCI_M_BACK_TO_BACK_ENABLE 0x200 |
| #define PCI_M_BASE_ADDRESS_BITS_31_4 0xFFFFFFF0 |
| #define PCI_M_BASE_ADDRESS_MEM_IO 0x1 |
| #define PCI_M_BASE_ADDRESS_PREFETCHABLE 0x8 |
| #define PCI_M_BASE_ADDRESS_TYPE 0x6 |
| #define PCI_M_BUS_MASTER_ENABLE 0x4 |
| #define PCI_M_DATA_PARITY_DETECT 0x100 |
| #define PCI_M_DETECT_PE 0x8000 |
| #define PCI_M_DEVSEL_TIMING 0x600 |
| #define PCI_M_FAST_BB_CAPABLE 0x80 |
| #define PCI_M_INVAL_ENABLE 0x10 |
| #define PCI_M_IO_ENABLE 0x1 |
| #define PCI_M_MEM_ENABLE 0x2 |
| #define PCI_M_PALETTE_SNOOP_ENABLE 0x20 |
| #define PCI_M_PARITY_ENABLE 0x40 |
| #define PCI_M_PCI_NODE_NUMBER_BUS 0xFF00 |
| #define PCI_M_PCI_NODE_NUMBER_DEVICE 0xF8 |
| #define PCI_M_PCI_NODE_NUMBER_FUNCTION 0x7 |
| #define PCI_M_PCI_NODE_NUMBER_OFFSET 0xFFFF0000 |
| #define PCI_M_RCV_MASTER_ABORT 0x2000 |
| #define PCI_M_RCV_TARGET_ABORT 0x1000 |
| #define PCI_M_SERR_ENABLE 0x100 |
| #define PCI_M_SIGNAL_SERR 0x4000 |
| #define PCI_M_SIGNAL_TARGET_ABORT 0x800 |
| #define PCI_M_SPECIAL_CYCLE_ENABLE 0x8 |
| #define PCI_M_WAIT_CYCLE_ENABLE 0x80 |
| #define PCIERR_K_LENGTH 72 |
| #define PCIFLAGS_M_DATA_PARITY_DETECT 0x1 |
| #define PCIFLAGS_M_DETECT_PE 0x20 |
| #define PCIFLAGS_M_FILL1 0xFFFFFF00 |
| #define PCIFLAGS_M_FILL2 0xC0 |
| #define PCIFLAGS_M_FILL3 0xFFFFFF00 |
| #define PCIFLAGS_M_RCV_MASTER_ABORT 0x8 |
| #define PCIFLAGS_M_RCV_TARGET_ABORT 0x4 |
| #define PCIFLAGS_M_SIGNAL_SERR 0x10 |
| #define PCIFLAGS_M_SIGNAL_TARGET_ABORT 0x2 |
