00001 #ifndef pcidef_h 00002 #define pcidef_h 00003 00004 #define PCI_K_VENDOR_ID 0 00005 #define PCI_K_DEVICE_ID 2 00006 #define PCI_K_COMMAND 4 00007 #define PCI_M_IO_ENABLE 0x1 00008 #define PCI_M_MEM_ENABLE 0x2 00009 #define PCI_M_BUS_MASTER_ENABLE 0x4 00010 #define PCI_M_SPECIAL_CYCLE_ENABLE 0x8 00011 #define PCI_M_INVAL_ENABLE 0x10 00012 #define PCI_M_PALETTE_SNOOP_ENABLE 0x20 00013 #define PCI_M_PARITY_ENABLE 0x40 00014 #define PCI_M_WAIT_CYCLE_ENABLE 0x80 00015 #define PCI_M_SERR_ENABLE 0x100 00016 #define PCI_M_BACK_TO_BACK_ENABLE 0x200 00017 #define PCI_K_STATUS 6 00018 #define PCI_M_FAST_BB_CAPABLE 0x80 00019 #define PCI_M_DATA_PARITY_DETECT 0x100 00020 #define PCI_M_DEVSEL_TIMING 0x600 00021 #define PCI_M_SIGNAL_TARGET_ABORT 0x800 00022 #define PCI_M_RCV_TARGET_ABORT 0x1000 00023 #define PCI_M_RCV_MASTER_ABORT 0x2000 00024 #define PCI_M_SIGNAL_SERR 0x4000 00025 #define PCI_M_DETECT_PE 0x8000 00026 #define PCI_K_REVISION_ID 8 00027 #define PCI_K_PROGRAMMING_IF 9 00028 #define PCI_K_SUB_CLASS 10 00029 #define PCI_K_BASE_CLASS 11 00030 #define PCI_K_CACHE_LINE_SIZE 12 00031 #define PCI_K_LATENCY_TIMER 13 00032 #define PCI_K_HEADER_TYPE 14 00033 #define PCI_K_BIST 15 00034 #define PCI_K_BASE_ADDRESS_0 16 00035 #define PCI_K_BASE_ADDRESS_1 20 00036 #define PCI_K_BASE_ADDRESS_2 24 00037 #define PCI_K_BASE_ADDRESS_3 28 00038 #define PCI_K_BASE_ADDRESS_4 32 00039 #define PCI_K_BASE_ADDRESS_5 36 00040 #define PCI_K_CARDBUS_CIS 40 00041 #define PCI_K_SUB_VNDR 44 00042 #define PCI_K_SUB_ID 46 00043 #define PCI_K_EXP_ROM_BASE 48 00044 #define PCI_K_INTR_LINE 60 00045 #define PCI_K_INTR_PIN 61 00046 #define PCI_K_MIN_GNT 62 00047 #define PCI_K_MAX_LAT 63 00048 #define PCI_S_PCIDEF 64 00049 #define PCI_K_DEVSEL_FAST 0 00050 #define PCI_K_DEVSEL_MEDIUM 1 00051 #define PCI_K_DEVSEL_SLOW 2 00052 #define PCI_K_NOT_IMPLEMENTED 0 00053 #define PCI_K_MASS_STORAGE_CTRLR 1 00054 #define PCI_K_NETWORK_CTRLR 2 00055 #define PCI_K_DISPLAY_CTRLR 3 00056 #define PCI_K_MULTIMEDIA_DEVICE 4 00057 #define PCI_K_MEMORY_CTRLR 5 00058 #define PCI_K_BRIDGE_DEVICE 6 00059 #define PCI_K_UNDEFINED 255 00060 #define PCI_K_SCSI_CTRLR 0 00061 #define PCI_K_IDE_CTRLR 1 00062 #define PCI_K_FLOPPY_CTRLR 2 00063 #define PCI_K_IPI_CTRLR 3 00064 #define PCI_K_OTHER_MASS_STORAGE 80 00065 #define PCI_K_NI_CTRLR 0 00066 #define PCI_K_TOKEN_CTRLR 1 00067 #define PCI_K_FDDI_CTRLR 2 00068 #define PCI_K_OTHER_NETWORK 80 00069 #define PCI_K_VGA_CTRLR 0 00070 #define PCI_K_XGA_CTRLR 1 00071 #define PCI_K_OTHER_DISPLAY 80 00072 #define PCI_K_VIDEO_CTRLR 0 00073 #define PCI_K_AUDIO_CTRLR 1 00074 #define PCI_K_OTHER_MULTIMEDIA 80 00075 #define PCI_K_RAM 0 00076 #define PCI_K_FLASH 1 00077 #define PCI_K_OTHER_MEMORY 80 00078 #define PCI_K_HOST_BRIDGE 0 00079 #define PCI_K_ISA_BRIDGE 1 00080 #define PCI_K_EISA_BRIDGE 2 00081 #define PCI_K_MC_BRIDGE 3 00082 #define PCI_K_PCI_PCI_BRIDGE 4 00083 #define PCI_K_PCMCIA_BRIDGE 5 00084 #define PCI_K_OTHER_BRIDGE 80 00085 #define PCI_K_INTR_PIN_NOT_USED 0 00086 #define PCI_K_INTR_PIN_INTA 1 00087 #define PCI_K_INTR_PIN_INTB 2 00088 #define PCI_K_INTR_PIN_INTC 3 00089 #define PCI_K_INTR_PIN_INTD 4 00090 #define PCI_K_MAX_DEVICES 32 00091 #define PCI_K_LENGTH 64 00092 00093 #define PCI_M_BASE_ADDRESS_MEM_IO 0x1 00094 #define PCI_M_BASE_ADDRESS_TYPE 0x6 00095 #define PCI_M_BASE_ADDRESS_PREFETCHABLE 0x8 00096 #define PCI_M_BASE_ADDRESS_BITS_31_4 0xFFFFFFF0 00097 00098 #define BASE_ADDR_32 0 00099 #define BASE_ADDR_BELOW_1MB 1 00100 #define BASE_ADDR_64 2 00101 #define BASE_ADDR_RESERVED 3 00102 #define PCI_M_PCI_NODE_NUMBER_FUNCTION 0x7 00103 #define PCI_M_PCI_NODE_NUMBER_DEVICE 0xF8 00104 #define PCI_M_PCI_NODE_NUMBER_BUS 0xFF00 00105 #define PCI_M_PCI_NODE_NUMBER_OFFSET 0xFFFF0000 00106 00107 #define PCIERR_K_LENGTH 72 00108 00109 #define PCIFLAGS_M_FILL1 0xFFFFFF00 00110 #define PCIFLAGS_M_DATA_PARITY_DETECT 0x1 00111 #define PCIFLAGS_M_SIGNAL_TARGET_ABORT 0x2 00112 #define PCIFLAGS_M_RCV_TARGET_ABORT 0x4 00113 #define PCIFLAGS_M_RCV_MASTER_ABORT 0x8 00114 #define PCIFLAGS_M_SIGNAL_SERR 0x10 00115 #define PCIFLAGS_M_DETECT_PE 0x20 00116 #define PCIFLAGS_M_FILL2 0xC0 00117 #define PCIFLAGS_M_FILL3 0xFFFFFF00 00118 00119 #define ERRTAG_K_PCIERR 16 00120 00121 struct _pci { 00122 short int pci_w_vendor_id; 00123 short int pci_w_device_id; 00124 union { 00125 short int pci_w_command; 00126 struct { 00127 unsigned pci_v_io_enable : 1; 00128 unsigned pci_v_mem_enable : 1; 00129 unsigned pci_v_bus_master_enable : 1; 00130 unsigned pci_v_special_cycle_enable : 1; 00131 unsigned pci_v_inval_enable : 1; 00132 unsigned pci_v_palette_snoop_enable : 1; 00133 unsigned pci_v_parity_enable : 1; 00134 unsigned pci_v_wait_cycle_enable : 1; 00135 unsigned pci_v_serr_enable : 1; 00136 unsigned pci_v_back_to_back_enable : 1; 00137 unsigned pci_v_command_fill : 6; 00138 }; 00139 }; 00140 union { 00141 short int pci_w_status; 00142 struct { 00143 unsigned pci_v_status_fill : 7; 00144 unsigned pci_v_fast_bb_capable : 1; 00145 unsigned pci_v_data_parity_detect : 1; 00146 unsigned pci_v_devsel_timing : 2; 00147 unsigned pci_v_signal_target_abort : 1; 00148 unsigned pci_v_rcv_target_abort : 1; 00149 unsigned pci_v_rcv_master_abort : 1; 00150 unsigned pci_v_signal_serr : 1; 00151 unsigned pci_v_detect_pe : 1; 00152 }; 00153 }; 00154 char pci_b_revision_id; 00155 char pci_b_programming_if; 00156 char pci_b_sub_class; 00157 char pci_b_base_class; 00158 char pci_b_cache_line_size; 00159 char pci_b_latency_timer; 00160 char pci_b_header_type; 00161 char pci_b_bist; 00162 int pci_l_base_address_0; 00163 int pci_l_base_address_1; 00164 int pci_l_base_address_2; 00165 int pci_l_base_address_3; 00166 int pci_l_base_address_4; 00167 int pci_l_base_address_5; 00168 int pci_l_cardbus_cis; 00169 short int pci_w_sub_vndr; 00170 short int pci_w_sub_id; 00171 int pci_l_exp_rom_base; 00172 int pci_l_reserved_3; 00173 int pci_l_reserved_4; 00174 char pci_b_intr_line; 00175 char pci_b_intr_pin; 00176 char pci_b_min_gnt; 00177 char pci_b_max_lat; 00178 }; 00179 00180 struct _base_address { 00181 union { 00182 int pci_l_base_address; 00183 struct { 00184 unsigned pci_v_base_address_mem_io : 1; 00185 unsigned pci_v_base_address_type : 2; 00186 unsigned pci_v_base_address_prefetchable : 1; 00187 unsigned pci_v_base_address_bits_31_4 : 28; 00188 }; 00189 }; 00190 }; 00191 00192 struct _pci_node_number { 00193 union { 00194 int pci_l_pci_node_number; 00195 struct { 00196 unsigned pci_v_pci_node_number_function : 3; 00197 unsigned pci_v_pci_node_number_device : 5; 00198 unsigned pci_v_pci_node_number_bus : 8; 00199 unsigned pci_v_pci_node_number_offset : 16; 00200 }; 00201 }; 00202 }; 00203 00204 struct _pci_busarray_hardware_id { 00205 union { 00206 long long pci_q_pci_hardware_id; 00207 struct { 00208 short int pci_w_pci_hardware_id_vendor; 00209 short int pci_w_pci_hardware_id_device; 00210 union { 00211 int pci_l_pci_hardware_id_fill; 00212 struct { 00213 short int pci_w_pci_hardware_id_sub_vndr; 00214 short int pci_w_pci_hardware_id_sub_id; 00215 }; 00216 }; 00217 }; 00218 }; 00219 }; 00220 00221 struct _pcierr { 00222 unsigned pcierr_v_fill1 : 11; 00223 unsigned pcierr_v_device_number : 5; 00224 unsigned char pcierr_b_bus_number; 00225 unsigned char pcierr_b_fill2; 00226 unsigned int pcierr_l_frame_size; 00227 struct _pci pcierr_r_pci; 00228 }; 00229 00230 struct _pciflags { 00231 union { 00232 struct { 00233 unsigned char pciflags_b_pciflags; 00234 unsigned pciflags_v_fill1 : 24; 00235 }; 00236 struct { 00237 unsigned pciflags_v_data_parity_detect : 1; 00238 unsigned pciflags_v_signal_target_abort : 1; 00239 unsigned pciflags_v_rcv_target_abort : 1; 00240 unsigned pciflags_v_rcv_master_abort : 1; 00241 unsigned pciflags_v_signal_serr : 1; 00242 unsigned pciflags_v_detect_pe : 1; 00243 unsigned pciflags_v_fill2 : 2; 00244 unsigned pciflags_v_fill3 : 24; 00245 }; 00246 }; 00247 }; 00248 00249 #endif 00250 00251
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